Four CAM Traps That Stop a Board Before It Is Made

Most designers treat CAM review as a formality once the schematic is done and the CAD DRC is green. Then the fabricator sends an engineering query (EQ) and the clock stops.

CAM review is not a second DRC. DRC asks whether the layout obeys the rules you typed into KiCad or Altium. CAM asks whether the same layout can be drilled, plated, printed, routed, and depanelized with the process that will actually run. The netlist is usually fine. What fails is the handshake between files: Gerber or ODB++ artwork, the order form, the panel drawing, and a PDF exported last week.

The four problems below show up on prototype cards and on production panels, on two-layer boards and on multilayer jobs, with HASL or ENIG, with a factory array or a customer-built panel and no process rail. None of them requires HDI. All of them are cheaper to fix in the design package than after lamination.

The single most common reason a job does not release is that two official documents disagree. Typical mismatches:

The board outline in the mechanical layer (often named GKO or GM1) does not match the dimensions typed on the order, or an old outline layer was left in the ZIP. A 126 × 145 mm board arrived with a leftover outline that did not close on those numbers. CAM cannot pick a contour until one file is declared master.

The order form says vias are tented; the solder-mask Gerber opens every via to the drill diameter. Or the reverse: the form says open vias, the mask covers them. HASL then either floods the hole or leaves bare copper rings that the designer did not expect.

A PDF panel drawing shows 2 mm routing slots. The Gerber mechanical layer shows only stamp holes. The order form says “route.” Three documents, two methods, zero process edge — so CAM cannot add slots without cutting into the customer outline.

Silkscreen text was drawn on the outline layer instead of the legend layer. Etch text was drawn 1 mil wide, which will not survive etch. Half-holes (castellations) were drawn but never declared plated or non-plated. Hole attributes wander in the same way: a drill marked PTH with a pad equal to the hole, or copper on one side only, leaves CAM no legal annular ring.

Treat one document as law and make the others quote it. A practical rule: the fabrication notes own process intent (tenting, plating, separation method, tolerance). The Gerber set owns geometry. If they fight, CAM will not guess. See Figure 1.

Figure 1 (fig1-notes-vs-gerber.png): Same job, two instructions. Left: mask layer open to the drill. Right: order note “tent all vias.”  . The job cannot be released until one side wins.

Write the process rules in one short block, not as scattered CAD comments:

Finished thickness and copper weight, called out separately for start foil and finished copper if they differ. Via treatment as a global rule plus exceptions (“all vias tented both sides except test vias marked in the keep-out layer”). PTH versus NPTH for every hole class, including castellations and tooling holes. Separation method: customer array or factory panel; V-score, route, or stamp holes; whether a process rail exists. Outline source: “use GKO, ignore old_GKO.” Dimensional tolerance only if you need tighter than the shop default — and only after you have asked whether the shop can hold it. A ±0.10 mm contour callout on a scored 1.0 mm panel is often tighter than a pooling line will sign.

Boards are cheap enough that many designers panelize at home: 2×1, 3×2, 1×3 on a large blank, often with zero process edge. The array looks efficient in CAD. In the shop it has to survive surface finish, electrical test, handling, and shipping, then come apart without tearing copper.

Three patterns keep stopping release.

Missing stamp holes on solid tabs. A 520 × 242 mm array with V-score only and no mouse-bites on the ribs will flex like a living hinge. On 1.6 mm FR-4 that is already risky; on 1.0 mm stock it is a breakage lottery. Add a row of 0.8 mm or 1.0 mm stamp holes across every connecting tab. V-score defines the bend line. Stamp holes define where the tab is allowed to fail.

Tabs that are too narrow. A 3×4 array of mid-size boards on 1.0 mm stock with skinny webs will crack in the panel, not at the desk. If you skip a process rail, the tabs are the only structure the panel has. Size them as structure, not as leftover copper.

Gerber and drawing disagree on how the array opens. Stamp holes and routed slots are not interchangeable. Routing needs a real gap — 2.0 mm is a workable minimum for a 1.6 mm board and a standard bit. If the Gerber has no gap and no rail, the shop cannot invent a slot without changing your outline. Pick one method, draw it in the mechanical layer, and repeat it in the notes. Duplicate or overlapping V-score lines are the same class of error: the panel is not rigid in the machine.

If the part is smaller than about 25 × 15 mm, do not assume V-score alone will give a clean edge. Small boards almost always need stamp holes or a routed array with a rail. A longer walk through the same panel, score, and outline questions — process edge, stamp-hole rows, copper on the score — is collected in this production note on panelization, V-cut, and edge clearance.

Figure 2 (fig2-panel-tabs.png): no stamp holes in the arrow indicated tab-routings.

Contour routing and V-scoring both remove material. Anything that sits in the tool path becomes burr, exposed copper, or a lifted pad. Designers often use one clearance for every edge. Shops cannot.

A workable pair of numbers on standard 1.6 mm FR-4 is: keep copper and pads at least 0.20 mm from a routed outline, and at least 0.35 mm from a V-score line. On thin boards (1.0 mm) and on large panels with no rail, add margin — 0.30 mm and 0.40–0.50 mm respectively. A 4 mil pad-to-outline gap that looks fine in the 2D viewer will show raw copper after the score opens.

Pull-back is cheaper than a respin. If a pad must live near the edge (an edge connector, a mounting pad, a copper pour used as a shield), say so in the notes and accept that the shop may clip the pour rather than the pad. Production markings and date codes also need a reserved patch that is not on copper and not on a score. See Figure 3.

Solder mask is where jobs look finished in CAD and then fail at assembly.

Tent versus open must be one rule. If the note says “tent vias,” the mask openings over those vias must be closed, or closed enough that the process can tent them. An opening equal to the drill diameter is not tenting; it is an open via with extra ink around the hole. Mixed treatment is allowed — test vias open, stitching vias tented — but only if the exception is named in the notes and visible in the mask layers. Do not leave CAM to infer intent from a 50/50 mix.

Mask bridges have a physical width. A 4 mil pad-to-pad gap on 1 oz copper will not hold a reliable dam after compensation and registration. In practice, 7–8 mil between SMT pads is the range that still prints as a bridge on a pooling line. In a BGA neighborhood the same math gets worse when the outer copper is 2 oz: etch compensation eats the space you thought you had, and a 6–7 mil gap designed under 1 oz rules will not survive. Either widen the gap, switch the dense pads to solder-mask-defined pads, or open the window entirely and accept a gang opening.

Large PTH holes need mask openings. A 3.1 mm plated hole with no mask clearance will collect ink on the pad. The hole solders badly and HASL cannot wet it cleanly. Vias you want tented should lose their openings; connector holes and test points should keep them.

Legend does not belong on copper you will solder. Silkscreen on a pad kills wetting. Move the reference designator, or drop it. Character height around 0.8 mm with a line width that the printer can hold is more useful than a beautiful font that sits on the land.

See Figure 4. The same four mask-and-via collisions — bridge width, tenting versus open windows, resin-plug notes that fight the Gerber, paste openings that do not match the mask — are grouped by EQ type in this CAM note on solder mask and via treatments.

Put the four traps on one quiet job so the interactions are visible.

Board: 126 × 145 mm, two-layer FR-4, 1.6 mm, 1 oz, ENIG, green mask, white legend. Customer array 2×1, V-score plus tabs, no process rail. Minimum drill 0.3 mm. The schematic is a power-and-IO card. DRC is clean.

CAM opens the ZIP and finds an old outline layer that does not match 126 × 145 mm. Several 0.3 mm holes have pads the same diameter as the drill, so there is no annular ring to plate. The order form says tent vias; the mask layer opens them. Two SMD rows sit 4 mil apart. A pour runs to within a few mils of the V-score. The tabs have no stamp holes.

None of these is a schematic error. Together they block release. The fix set is equally ordinary: delete the stale outline, grow PTH pads, close the via openings or change the note, widen or open the dense mask gaps, pull copper back from the score, and put mouse-bites on the tabs. That is a same-day EQ cycle, not a new layout — if the designer is available to answer.

Swap the stackup for four or six layers and the same four emails still go out. Impedance notes add a fifth argument, but they do not retire the outline, the panel, the edge, or the mask.

Run this on every fabrication package. If any line is false, the ZIP is not ready.

 

Boards fail in CAM for boring reasons, which is good news: the fixes are also boring. Make the files tell one story. Draw how the panel comes apart. Keep copper off the tool. Make the solder-mask layer describe the process you named in the notes.

Do that before you upload, and the EQ — if it comes at all — is a confirmation, not a reconstruction of the job. The schematic can stay exactly as it is. The package around it should not.